Software programmable and AI Capable FPGAs

In the spring, Xilinx CEO Victor Penn introduced the concept of the Adaptive Compute Acceleration Platform (ACAP). At the Xilinx Developer Forum in San Jose, he introduced the first two ACAP families called Versal and showed what they can do. And that is remarkable.

Xilinx promises to build no less than an adaptable, intelligent world with the new programmable logic family »Versal«. At the Xilinx Developer Forum in San Jose, the California-based FPGA specialist lifted the veil and let the first insights into actual products. 

The Versal ACAPs combine scalable processor engines, adaptive hardware engines and so-called intelligent engines with advanced storage and interface technologies to accelerate any application in a powerful and heterogeneous way. An important requirement in the development of ACAP was that the hardware and software of the Versal ACAPs could be programmed and optimized by software developers, data specialists and hardware developers. There are a variety of tools, software, libraries, IP, middleware and frameworks that allow design processes in accordance with industry standards. 

Based on TSMC's 7nm FinFET process technology, the Versal portfolio is the first platform to combine software programmability with domain-specific hardware acceleration and the necessary adaptability to keep up with today's fast-paced pace of innovation. The product range includes six families of ACAP building blocks designed to have scalability and inference based on artificial intelligence (inference) across a wide range of applications across markets, from the cloud, through networks and wireless communications, to edge computing and endpoints. 

With the explosion of AI and Big Data and the demise of Moore's Law, the industry has reached a critical turning point. The design cycles of silicon can not keep pace with the pace of innovation, "Peng said. »We've spent four years developing Versal, the sector’s first ACAP. It's exactly what the sector needs, when it's needed. " 

The Versal ACAPs combine scalar processor engines, adaptive hardware engines and so-called intelligent engines with advanced storage and interface technologies.

The Versal Roadmap initially envisages two family strands: the »Prime Series« and the »AI Core Series«. While the Prime Series, which includes three families of Prime, Premium and High Bandwidth Memory (HBM), the AI Core series from AI Core, optimized for AI applications, consists of AI Core, AI Edge and AI RF. A new hardware block was developed in the AI ​​Core series, and integrated with the AI ​​Engine. It is designed to meet the emerging low-latency AI inference requirements for a variety of applications and also supports digital signal processing (DSP) functions which are typical for mobile and radar applications. The AI ​​Engines are tightly coupled with the Versal Adaptable Hardware Engines to accelerate the overall processing of data. This means that both hardware and software can be tuned for maximum performance and efficiency. 

The Versal Prime Series and the Versal KI Core series, as the first representatives of the Versal generation of ACAP chips, are on the market.

(This paper is a translation)